Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb / s Optical Receivers

The design of distributed amplifiers (DAs) is one of the challenging aspects in emerging ultra high bit rate optical communication systems. This is especially important when implementation in submicron silicon complementary metal oxide semiconductor (CMOS) process is considered. This work presents a novel design scheme for DAs suitable for frontend amplification in 40 and 100 Gb/s optical receivers. The goal is to achieve high flat gain and low noise figure (NF) over the ultra wideband operating bandwidth (BW). The design scheme combines shifted second tire (SST) matrix configuration with cascode amplification cell configuration and uses m-derived technique. Performance investigation of the proposed DA architecture is carried out and the results are compared with that of other DA architectures reported in the literature. The investigation covers the gain and NF spectra when the DAs are implemented in 180, 130, 90, 65 and 45 CMOS standards.The simulation results reveal that the proposed DA architecture offers the highest gain with highest degree of flatness and low NF when compared with other DA configurations. Gain-BW products of 42772 and 21137 GHz are achieved when the amplifier is designed for 40 and 100 Gb/s operation, respectively, using 45 nm CMOS standard. The simulation is performed using AWR Microwave Office (version 10).

ISSN 2277-3061 5662 | P a g e F e b r u a r u r y 2 8 , 2 0 1 5

1-INTRODUCTION
Everybody wants to benefit from the evaluation in the field of communication especially through internet. Due to the expanding demand of communication services, the volume of data exchanged in the communication systems has increased. This leads to increase data rate of the global communication systems from tens of Gb/s to Tb/s. BW requirements will increase by more than 100 times and applications such as virtual reality require data rate that are 10,000 times higher than currently available. To transport such data rate, a media with low loss and high BW is required [1, 2]. Among the available medium to transfer the data, optical fibers have the best performance. Optical fibers are very common these days to transport very high rate digital data. Such high speed data rates can be transported over kilometers of optical fiber and without significant loss. Normally loss is very low when the signal is transmitted using light rather than electrical signal. These fibers also have the advantage of being low cost in addition to improvement of performance. Fiber optic devices and systems are evidently employed to realize very high data rates. Fiber optic communication is a solution because high data rates can be transmitted through this high capacity cable with high performance [3].
The exponential growth of Internet traffic is fueling the research and development of wavelength division multiplexed passive optical network technology in the access network segment [4]. Driven by the continues increase in BW demand and number of subscribers, future access networks will require 40 Gb/s high speed service per wavelength channel [5,6] on a 50 GHz dense wavelength grid. The realization of high-speed analog-to-digital conversation and digital signal processing have enabled a bit rate of 100 Gb/s in long-haul coherent optical communication system [7]. However, for short-reach 100 Gb/s applications, solutions that use intensity modulation and direction detection are seen as more practical [8]. With the advances in semiconductor technologies, integrated circuits operating at 40 Gb/s have been realized in standard CMOS process [9]. Among all kinds of high speed circuits, the broadband amplifier is a key building block at both the transmitting and receiving ends, see Fig. 1. In fact there is demand for wideband CMOS amplifiers in the frontend section of the optical receivers. Distributed amplification is one of the well-known methods to provide such performance by absorbing the parasitic capacitances of parallel gain distributed cell into an artificial transmission line, which in return, guarantees the gain uniformity and input/output matching within the BW of operation. However, design DA for 40 Gb/s (and above) optical receivers needs careful consideration related to the gain, frequency spectrum and NF.This paper addresses the design issues and performance investigation of CMOS DA for the front-end amplification stage in 40 and 100 Gb/s optical receivers.

2-RELATED WORK
In 2005, Wolf et al [11] demonstrated an eight-stage DA with 12.5 dB ± 0.45 dB gain and 50 GHz BW in a commercially available 0.1 μm metamorphic GaAs HEMT technology. The amplifier has a minimum NF lower than 2.5 dB in the BW. The group delay variation from 9 to 40 GHz is ± 7.5 ps and circuit power consumption is 0.4 W. Such amplifier packaged with a high responsively PD into a fiber pig-tailed module. Eye diagrams measurements demonstrate the successful highspeed operation of the photoreceiver.
In 2007, Chien and Lu [12] presented a novel circuit topology for high-gain 40 Gb/s DAs. Based on the conventional distributed architecture, the gain cells were realized by cascading cascode stages for gain enhancement. In addition, the stagger-tuning technique was extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating BW and the gain flatness. With the proposed circuit architecture, two amplifiers were implemented in a standard 180 nm CMOS technology. The amplifier with a 3 x3 configuration exhibits a gain of 16.2 dB and a 3 dB BW of 33.4 GHz, while the one in a form of 2x4 demonstrates a gain of F e b r u a r u r y 2 8 , 2 0 1 5 20 dB and a BW of 39.4 GHz. Consuming a DC power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence at 40 Gb/s. [13] presented a circuit technique to compensate for the metal and substrate loss of the onchip transmission lines, and, consequently, to improve the gain flatness and BW of CMOS DAs for optical receivers. An eight-stage DA suitable for 40 Gb/s optical communication was devised and implemented in a 130 nm CMOS process. The DA achieves a flat gain of 10 dB from DC to 44 GHz with an input and output matching better than −8 dB. The measured NF varies from 2.5 to 7.5 dB with the amplifier"s band. The proposed DA dissipates 103mW from two 1-V and 1.2-V DC supplies.

In 2009, Moez and Elmasry
In 2009, Entesari et al [14] presented a state-of-the-art DA with coupled inductors in the gate line. The proposed coupled inductors, in conjunction with series-peaking inductors in cascode gain stages, provide BW extension with flat gain response for the amplifier without any additional power consumption. On the other hand, gate-inductor coupling improves the input matching of the amplifier considerably. The detailed analysis and design methodology for the proposed DA were presented. The new four-stage DA, fabricated using an IBM 0.18-m CMOS process, achieves a power gain of around 10 dB, input and output return losses better than 16 and 18 dB, respectively, a NF of 3.6-4.9 dB, and a power consumption of 21mW over a 16-GHz flat 1-dB BW. is between 0.1 and 3.75 dBm across the entire band.
In 2010, Ghadiri and Moez [15] presented a new high-gain structure for DA. Negative capacitance cells were exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the DA while keeping the desired BW. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplifier BW. Implemented in 130 nm IBM"s CMRF8SF CMOS, the proposed six-stage DA presents an average gain of 13.2 dB over a BW of 29.4 GHz. The measured input return loss is less than 9 dB and the output return loss is less than 9.5 dB over the entire BW. With a chip area of 1.5 mm X 0.8 mm, the amplifier consumes 136 mW from a 1.5-V DC power supply.
In 2010, Chien et al [16] presented a transimpedance amplifier (TIA) with a tunable BW for optical communications. The proposed TIA is composed of two cascaded stages in which an input network with inductive peaking elements is employed in the first stage for broadband operations while a modified DA is utilized as the second stage for enhanced transimpedance gain. In addition, a feedback loop is incorporated as the bandwidth-tuning mechanism. By tuning the BW of the TIA, optimum circuit operation with lowest bit error rate (BER) can be achieved in the receiver front end for highspeed data transmission. The proposed circuit was implemented in a 180 nm CMOS process. Consuming a DC power of 33.3 mW from a 1.8-V supply, the fabricated TIA exhibits a transimpedance gain of 47.8 dB and a variable 3-dB BW from 6.2 to 10.5 GHz. Providing a -1 pseudorandombit sequence at 9-15 Gb/s, a BER less than was demonstrated experimentally by the TIA with the BW tuning mechanism.
In 2011, KimandBuckwalter [17] demonstrated a low-power cascode DA in a 45 nm silicon-on-insulator (SOI) CMOS process. The amplifier achieves a 3 dB BW of 92 GHz. The peak gain is 9 dB with a gain-ripple of less 1.5 dB over the BW. The group-delay variation is under ± 4.7ps over the 3 dB BW. The amplifier consumes 73.5mW from a 1.2V supply and results in a GBW efficiency figure of merit of 3.53 GHz/mW. The chip occupies an area of 0.45 including the pads.
In 2012, Jahanian and Heydari [18] presented a CMOS DA with distributed active input balun that achieves a GBW product of 818 GHz, while improving linearity. Each cell within the DA employs dual-output two-stage topology that improves gain and linearity without adversely affecting BW and power. Comprehensive analysis and simulations were carried out to investigate gain, BW, linearity, noise, and stability of the proposed cell, and compare them with conventional cells. Fabricated in a 65-nm low-power CMOS process, the 0.9-mm DA achieves 22 dB of gain and a P1dB of 10 dBm, while consuming DC power of 97 mW from a 1.3-V supply. A distributed balun, designed and fabricated in the same process, using the same topology achieves a BW larger than 70 GHz and a gain of 4 dB with 19.5-mW power consumption from 1.3-V supply.
In 2013, Feng et al [19] realized compact self-biased wideband low noise amplifier (LNA) in Global Foundries 65 nm CMOS technology. Wideband input matching characteristic is achieved by placing a series gate inductor and a parallel tuning capacitor in the resistive-feedback network. Combined with the inductive-series peaking technique which further extends the BW, the proposed cascaded three-stage resistive-feedback amplifier obtains a large operating BW which is comparable with the DA. Measurement shows that the proposed amplifier achieves a power gain of with input and output return losses better than 8 dB and NF ranging from 4.5 to 6.8 dB between 2.1-39 GHz. The fabricated low LNA occupies a silicon area of 0.16 including all testing pads and draws 17 mA from a 1.5 V power supply.
In 2013, Kao et al. [20] proposed a new DA topology which is a combination of the conventional DA and the cascaded single-stage DA. This DA topology can provide wide BW with considerations of the gain, NF, and output power simultaneously, and requires reasonable DC power consumption. Two termination methods of this combination were investigated. From the measurements, the first DA has a small-signal gain of 20.5 dB, a 3-dB BW of 35 GHz, and a GBW product of 371 GHz. The maximum output power at 1-dB output compression point is 8.6 dBm and the NF is between 6.8-8 dB at frequencies lower than 18 GHz. The chip size, including testing pads, is only 0.78 mm, and the ratio of the GBW to chip size is 476GHz/mm. The second DA has a small-signal gain of 24dB, a 3-dB BW of 33 GHz, and a GBW product of 523 GHz. The maximum output power is 9 dBm and the NF is between 6.5-7.5 dB at frequencies lower than 18 GHz. The chip size including testing pads is only 0.83 mm, and the ratio of the GBW to chip size is 630 GHz mm. F e b r u a r u r y 2 8 , 2 0 1 5 In 2013, Cho et al. [21] proposed a wideband switchless bi-directional DA in a commercial 130 nm CMOS technology, which realizes multi-octave BW with high gain and low NF using DA technique and cascode amplifier pair. The measured gain is over 10 dB and measured NF is 3.2-6.5 dB. The input and output return losses are better than 9 dB at 3-20 GHz. The measured output power 1dB and output input power (OIP3) is larger than 8 dBm and 17 dBm at 4-15 GHz. The chip sizeis 0.96 x 0.85 including pads. The proposed switchless bi-directional amplifier has almost the same chip size compared to the conventional uni-directional DA.
In 2014, Kim and Nguyen [22] presented a new tri-band power amplifier on a 180 nm SiGeBiCMOS process, operating concurrently in Ku/K/Ka and -band, is presented. The concurrent tri-band PA design is based on the DA structure with capacitive coupling to enable large device size, while maintaining wide BW, gain cells with the enhanced-gain peaking inductor, and negative-resistance active notch filters for improved tri-band gain response. The concurrent tri-band PA exhibits measured small-signal gain around 15.4, 14.7 and 12.3 dB in the low band (10-19 GHz), midband (23-29 GHz), and high band (33-40 GHz), respectively.
It is clear from the above survey that the reported designs of DAs suitable for high bit rate optical receiver don"t achieves simultaneously wide BW, high flat gain and low NF. This issue is addressed in this thesis where a modified DA topology is introduced to reach these goals.

3-PROPOSED DA ARCITECTURE AND DESIGN CONCEPTS
In the literature, different DA architectures have been discussed. Each one has its own design topology and uses different techniques to enhance one of the design requirements: wide BW, high flat gain and low NF. In this section, a new DA architecture is proposed to achieve ultrawide band operation under high amplification gain and low NF conditions. The proposed architecture collects the main features behind different topologies and techniques adopted in previous DA designs such as shifted second stage (SST) topology, matrix configuration, cascode cell amplifier configuration, and mderived matching technique. Design issues based on deep submicron CMOS technology are discussed toward achieving efficient front-end amplification in 40 Gb/s and 100 Gb/s optical receivers.

-Architecture of the Proposed Distributed Amplifier
The main idea behind the proposed DA is to combine high-feature topologies and techniques adopted by other DA designs. The task in this work is primarily to design CMOS-based DA with ultrawide BW, high flat gain and low NF suitable for high bit rate optical receivers ( 40 Gb/s). The proposed DA uses the following techniques and topologies a-m-derived technique m-derived techniques is used at the input and output of constant-k filter sections in order to obtain flat BW and constant impedance matching.

b-Shifted-Second Tire Matrix Configuration
This type of DA uses additive and multiplicative technique to achieve high flat gain. The configuration uses M stages and N distributed cells (N tires). Simulation results show that design the DA with two stages and four distributed cells is sufficient to get the require design target. Using M>2 and N>4 will increase the complexity of the design without offering reasonable performance improvement.

c-Cascode Amplification Cell Configuration
Cascode DA is obtained by adding common-gate amplifier section to the drain line of common-source amplifier stage. Using cascode amplification cells in DA configuration will decrease the variation of the capacitance seen by the transmission line and offer a nearly flat gain over wider BW as compared with the simple common-source amplifier.
The cascode amplifier can be considered as a two-stage amplifier composed of a transconductance amplifier followed by a current buffer [23]. Compared to a single amplifier stage, this combination may have one or more of the following characteristics: higher input-output isolation, higher input impedance, higher output impedance, higher gain or higher BW. Thus cascade configuration can be designed to improve input-output isolation (or reverse transmission) as there is no direct coupling from the output to the input. Note that the cascode amplifier behaves as a common-source amplifier with higher gain. If identical transistor is used, the ≈ . The input resistance of the cascode amplifier tends to infinitely since the input signal source is applied to the high impedance gate terminal.
The output resistance of the cascode amplifier is given by This yields higher output impedance compared with conventional common-source amplifier.

3.2-Design Concepts
The The next step is to determine transistor gate width for different submicron CMOS standards. The gate length (channel length) L is set equal to the used CMOS standard [24].The gate width is estimated using the following relation. is the oxide capacitance per unit area. Unfortunately, values of for submicron CMOS standards used in this thesis <180 nm are not reported in the literature. For example, Ref. [25] gives for CMOS standards 800, 500, 250 and 180 nm (see Table 1). These data are curve fitted to the flowing equation = + + (7) where is the CMOS standard in nm. The values of the fitting coefficients are = 0.017188 = -25.876 F e b r u a r u r y 2 8 , 2 0 1 5 = 12084 Fig. 6 shows the variation of with CMOS standard. The marks are the data taken for Ref. [25] while the solid line denotes curve fitting. The curve fitting is used to extract for CMOS standards 130, 90, 65 and 45 nm (see Table 1 and Fig. 7).  where is the gate area and is the permittivity of the sillicon oxide which has thickness. As CMOS standard decreases, thickness decreases too and leading to higher values for .
The dependence of the gate width on the cutoff frequency of the transmission line is reflected in Equ. 6b. For a given CMOS standard, the gate width is inversely proportional to the cutoff frequency. This relation is illustrated graphically in Fig. 8 where the gate width is plotted versus cutoff frequency for different values of CMOS standards. According to Equ. 6b, W Increases as CMOS standard decreases. Here is the electron mobility in the channel (assuming NMOS structure) and is the over drive voltage which is set to 0.2V in the simulation. With the aid of Equ. 6b one can arrive to the following expression for the transconductance = (9) Investigating Equ. 9 reveals the following findings I.
is independent of oxide capacitance and gate width .
II. is inversely proportion to both cutoff frequency and the square of the gate length.
The electron mobility for NMOS transistors fabricated with standards 180 nm and above are reported in Ref. [25] and listed in Table 2. These data is curve fitted to the following polynomial in order to extract the values of for standards below 180 nm (see Fig. 9 Table 3 lists the required transistor design parameters (L, W and ) for NMOS transistor fabricated using deep submicron standards and operates at a specific value of cutoff frequency . F e b r u a r u r y 2 8 , 2 0 1 5

4.1-Introduction
This section presents simulation results characterizing the gain, NF and BW of the proposed distributed amplifier for 40 and 100 Gb/s operation. The results are compared with the performance of five DA architectures, namely I. Conventional DA which uses common-source amplification cells.

II.
Cascode DA which uses cascode configuration for the amplification.
III. m-derived DA which is a conventional DA supported with both input and output m-derived stages.
IV. Matrix DA where the amplification cells are arranged in matrix-form topology.
All the DAs considered here are designed with four amplification cells per stage. The proposed DA, matrix and SST distributed amplifiers have two stages.
Simulation results related to DA characteristic are obtained using AWR Microwave Office (version 10). The results are then used to design the proposed DA for 40 and 100 Gb/s optical receivers.

4.2-Gain and Noise Figure Spectra
The aim of this section is to investigate the gain and NF spectra when the proposed DA is designed using different nano scale CMOS technologies. The results are to be compared with other DA architectures to assess the main features behind the proposed DA.   From the results illustrated in Fig. 11 and Tables 4 and 5 one can find out that the proposed DA the best results (highest gain and BW) when compared with other DAs. Conventional DA gives medium gain but not flat with low BW. Cascode DA gives low gain with BW range close to this work. M-derived DA gives flat medium gain with low BW. Matrix DA gives high gain but not flat with low BW. SST gives flat high gain with low BW.
The simulation is repeated to investigate the characteristics of 80 GHz-cut off frequency DAs suitable for around 100 Gb/s operation. The results are presented in Fig. 12 to highlight the gain spectrum and summarised in Tables 6 and 7 to assess the DC gain and BW, respectively, of various DAs synthesized with nanoscale CMOS standards.  Investigating the results in Fig 12 and Tables 6 and 7 reveals that the same conclusions drawn from the 35 GHz cutoff frequency DAs are also applied.
The results also show that when the cutoff frequency increases, the gain decreases for all DAs. However, the proposed DA gives the highest gain. One can apply these results to all standards (180, 130, 90, 65 and 45 nm).
The simulation is carried further to assess the NF spectrum of 35 GHzand 80 GHz cut off frequency DAs and the results are displayed in Figs

4.3-Effect of Transmission Line Cutoff Frequency
The cutoff frequency of drain and gate transmission lines is usually used as one of the main entry design parameters for DAs. This section illustrates the depends of DA characteristic on the cutoff frequency. The results are reported for various DA architectures and various CMOS standards. The investigation is focused on low-frequency gain, low-frequency NF, and 3 dB BW.
Figs. 15 a-e shows the dependence of the low-frequency gain on the line cutoff frequency for CMOS standards 180, 130, 90, 65 and 45 nm, respectively. Note that the proposed DA has the highest gain among the DAs considered here and this conclusion holds true for all cutoff frequency and CMOS standards. Note further that the amplifier gain decreases as the cutoff frequency increases. F e b r u a r u r y 2 8 , 2 0 1 5 Variation of low-frequency NF with cutoff frequency is given in Fig. 16. The results are reported for various DA configuration and CMOS standards. Investigation the results in this figure highlights the following findings. The proposed DA is characterized by relatively low NF over all values of cutoff frequency and CMOs standards. The calculation is carried further to estimate the 3 dB BW of the DAs and the results are displayed in Fig. 17

4.4-Designing the Proposed DAs for 40 and 100 Gb/s Operation
The results reported in the previous sections can be used as a guideline to design the proposed DA for front-end amplification in 40 Gb/s and 100 Gb/s optical receivers. The BW of the optical receiver is usually set equal to 0.7x bit rate as a hand of thumb estimate.
From Fig. 17, one can deduced the cutoff frequencies for various CMOs standards that can be used as a design parameter to achieve BWs corresponding to 40 and 100 Gb/s. This design parameter is used to deduce both geometric and characteristics parameters of the DAs. Tables 10 and 11